t8010: add H9P PCIe NVMe storage support #4
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| # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| %YAML 1.2 | ||
| --- | ||
| $id: http://devicetree.org/schemas/pci/apple,t8010-pcie.yaml# | ||
| $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
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| title: Apple H9P/T8010 PCIe Host Controller | ||
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| maintainers: | ||
| - Hector Martin <marcan@marcan.st> | ||
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| description: | ||
| Apple A10/T8010 devices use an older H9P PCIe root complex for the | ||
| internal storage path. It exposes one ECAM window shared by up to four | ||
| root ports, controller-specific PHY and port register windows, and a | ||
| controller-local MSI block. | ||
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There was a problem hiding this comment. Please mention complications with NVMMU regarding the storage device in the main description. |
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| allOf: | ||
| - $ref: /schemas/pci/pci-host-bridge.yaml# | ||
| - $ref: /schemas/interrupt-controller/msi-controller.yaml# | ||
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| properties: | ||
| compatible: | ||
| const: apple,t8010-pcie | ||
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| reg: | ||
| minItems: 10 | ||
| maxItems: 10 | ||
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| reg-names: | ||
| items: | ||
| - const: config | ||
| - const: phy0 | ||
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There was a problem hiding this comment. The second memory region 0x6_0000_0000 is |
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| - const: phy1 | ||
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There was a problem hiding this comment. There is only one phy, so this needs a better name. I believe this range corresponds to |
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| - const: phy2 | ||
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There was a problem hiding this comment. There is only one phy, so this needs a better name. I believe this range corresponds to |
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| - const: port0 | ||
| - const: port1 | ||
| - const: port2 | ||
| - const: port3 | ||
| - const: nvmmu0 | ||
| - const: pcieclk-postup | ||
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| interrupts: | ||
| description: | ||
| Four port state interrupts followed by 32 MSI interrupts and the | ||
| optional NVMMU fault interrupt for the active storage port. | ||
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There was a problem hiding this comment. Please use |
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| minItems: 37 | ||
| maxItems: 37 | ||
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There was a problem hiding this comment. maxItems without minItems implies identical minItems, so minItems here should be removed also for |
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| clocks: | ||
| minItems: 3 | ||
| maxItems: 3 | ||
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| clock-names: | ||
| items: | ||
| - const: core | ||
| - const: aux | ||
| - const: ref | ||
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| power-domains: | ||
| minItems: 3 | ||
| maxItems: 3 | ||
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| power-domain-names: | ||
| items: | ||
| - const: core | ||
| - const: aux | ||
| - const: ref | ||
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| reset-gpios: | ||
| description: | ||
| PERST# GPIOs indexed by PCIe root port. | ||
| minItems: 1 | ||
| maxItems: 4 | ||
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| clkreq-gpios: | ||
| description: | ||
| CLKREQ# GPIOs indexed by PCIe root port. | ||
| minItems: 1 | ||
| maxItems: 4 | ||
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| msi-controller: true | ||
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| msi-parent: true | ||
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| apple,msi-doorbell: | ||
| $ref: /schemas/types.yaml#/definitions/uint32 | ||
| description: | ||
| MSI doorbell address programmed into downstream endpoints. | ||
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| apple,enabled-ports: | ||
| $ref: /schemas/types.yaml#/definitions/uint32 | ||
| description: | ||
| Bitmask of root ports that should be powered and trained. | ||
| minimum: 1 | ||
| maximum: 15 | ||
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| apple,nvmmu-iova: | ||
| $ref: /schemas/types.yaml#/definitions/uint32 | ||
| description: | ||
| Base device-visible address for the reserved NVMMU/SART window. | ||
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| memory-region: | ||
| description: | ||
| Reserved physical window programmed into the H9P NVMMU/SART path. | ||
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There was a problem hiding this comment. This should be prefixed with When a node is referencing another node, please word like this in the description, |
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| maxItems: 1 | ||
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| interrupt-controller: true | ||
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| '#interrupt-cells': | ||
| const: 1 | ||
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There was a problem hiding this comment. Instead of hardcoding the port and port count, each port should be represented as a device tree node (similar to pcie-apple), then the driver should scan the nodes to determine the number of ports. This will be required for things like wifi to have a device tree node to store properties like firmware name. |
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| required: | ||
| - compatible | ||
| - reg | ||
| - reg-names | ||
| - interrupts | ||
| - clocks | ||
| - clock-names | ||
| - power-domains | ||
| - power-domain-names | ||
| - reset-gpios | ||
| - clkreq-gpios | ||
| - bus-range | ||
| - ranges | ||
| - msi-controller | ||
| - msi-parent | ||
| - apple,enabled-ports | ||
| - apple,nvmmu-iova | ||
| - memory-region | ||
| - '#interrupt-cells' | ||
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| unevaluatedProperties: false | ||
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| examples: | ||
| - | | ||
| #include <dt-bindings/gpio/gpio.h> | ||
| #include <dt-bindings/interrupt-controller/apple-aic.h> | ||
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| reserved-memory { | ||
| #address-cells = <2>; | ||
| #size-cells = <2>; | ||
| ranges; | ||
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| pcie0_nvmmu_window: nvmmu-window@8bee00000 { | ||
| reg = <0x8 0xbee00000 0x0 0x01200000>; | ||
| no-map; | ||
| }; | ||
| }; | ||
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| soc { | ||
| #address-cells = <2>; | ||
| #size-cells = <2>; | ||
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| pcie0: pcie@610000000 { | ||
| compatible = "apple,t8010-pcie"; | ||
| device_type = "pci"; | ||
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| reg = <0x6 0x10000000 0x0 0x1000000>, | ||
| <0x6 0x00000000 0x0 0x8000>, | ||
| <0x6 0x00008000 0x0 0x4000>, | ||
| <0x6 0x0a000000 0x0 0x40000>, | ||
| <0x6 0x01000000 0x0 0x4000>, | ||
| <0x6 0x02000000 0x0 0x4000>, | ||
| <0x6 0x03000000 0x0 0x4000>, | ||
| <0x6 0x04000000 0x0 0x4000>, | ||
| <0x6 0x01004000 0x0 0x4000>, | ||
| <0x6 0x00010000 0x0 0x8000>; | ||
| reg-names = "config", "phy0", "phy1", "phy2", | ||
| "port0", "port1", "port2", "port3", | ||
| "nvmmu0", "pcieclk-postup"; | ||
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| interrupt-parent = <&aic>; | ||
| interrupts = <AIC_IRQ 270 IRQ_TYPE_LEVEL_HIGH>, | ||
| <AIC_IRQ 273 IRQ_TYPE_LEVEL_HIGH>, | ||
| <AIC_IRQ 276 IRQ_TYPE_LEVEL_HIGH>, | ||
| <AIC_IRQ 279 IRQ_TYPE_LEVEL_HIGH>, | ||
| <AIC_IRQ 288 IRQ_TYPE_EDGE_RISING>, | ||
| <AIC_IRQ 289 IRQ_TYPE_EDGE_RISING>, | ||
| <AIC_IRQ 290 IRQ_TYPE_EDGE_RISING>, | ||
| <AIC_IRQ 291 IRQ_TYPE_EDGE_RISING>, | ||
| <AIC_IRQ 292 IRQ_TYPE_EDGE_RISING>, | ||
| <AIC_IRQ 293 IRQ_TYPE_EDGE_RISING>, | ||
| <AIC_IRQ 294 IRQ_TYPE_EDGE_RISING>, | ||
| <AIC_IRQ 295 IRQ_TYPE_EDGE_RISING>, | ||
| <AIC_IRQ 296 IRQ_TYPE_EDGE_RISING>, | ||
| <AIC_IRQ 297 IRQ_TYPE_EDGE_RISING>, | ||
| <AIC_IRQ 298 IRQ_TYPE_EDGE_RISING>, | ||
| <AIC_IRQ 299 IRQ_TYPE_EDGE_RISING>, | ||
| <AIC_IRQ 300 IRQ_TYPE_EDGE_RISING>, | ||
| <AIC_IRQ 301 IRQ_TYPE_EDGE_RISING>, | ||
| <AIC_IRQ 302 IRQ_TYPE_EDGE_RISING>, | ||
| <AIC_IRQ 303 IRQ_TYPE_EDGE_RISING>, | ||
| <AIC_IRQ 304 IRQ_TYPE_EDGE_RISING>, | ||
| <AIC_IRQ 305 IRQ_TYPE_EDGE_RISING>, | ||
| <AIC_IRQ 306 IRQ_TYPE_EDGE_RISING>, | ||
| <AIC_IRQ 307 IRQ_TYPE_EDGE_RISING>, | ||
| <AIC_IRQ 308 IRQ_TYPE_EDGE_RISING>, | ||
| <AIC_IRQ 309 IRQ_TYPE_EDGE_RISING>, | ||
| <AIC_IRQ 310 IRQ_TYPE_EDGE_RISING>, | ||
| <AIC_IRQ 311 IRQ_TYPE_EDGE_RISING>, | ||
| <AIC_IRQ 312 IRQ_TYPE_EDGE_RISING>, | ||
| <AIC_IRQ 313 IRQ_TYPE_EDGE_RISING>, | ||
| <AIC_IRQ 314 IRQ_TYPE_EDGE_RISING>, | ||
| <AIC_IRQ 315 IRQ_TYPE_EDGE_RISING>, | ||
| <AIC_IRQ 316 IRQ_TYPE_EDGE_RISING>, | ||
| <AIC_IRQ 317 IRQ_TYPE_EDGE_RISING>, | ||
| <AIC_IRQ 318 IRQ_TYPE_EDGE_RISING>, | ||
| <AIC_IRQ 319 IRQ_TYPE_EDGE_RISING>, | ||
| <AIC_IRQ 272 IRQ_TYPE_EDGE_RISING>; | ||
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| msi-controller; | ||
| msi-parent = <&pcie0>; | ||
| apple,msi-doorbell = <0xbffff000>; | ||
| apple,enabled-ports = <0x1>; | ||
| apple,nvmmu-iova = <0xbc000000>; | ||
| memory-region = <&pcie0_nvmmu_window>; | ||
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| #address-cells = <3>; | ||
| #size-cells = <2>; | ||
| #interrupt-cells = <1>; | ||
| bus-range = <0x00 0x0f>; | ||
| ranges = <0x03000000 0x0 0xc0000000 | ||
| 0x7 0xc0000000 0x0 0x40000000>; | ||
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| clocks = <&clkref>, <&clkref>, <&clkref>; | ||
| clock-names = "core", "aux", "ref"; | ||
| power-domains = <&ps_pcie>, <&ps_pcie_aux>, | ||
| <&ps_pcie_ref>; | ||
| power-domain-names = "core", "aux", "ref"; | ||
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| reset-gpios = <&pinctrl_ap 12 GPIO_ACTIVE_HIGH>; | ||
| clkreq-gpios = <&pinctrl_ap 16 GPIO_ACTIVE_HIGH>; | ||
| }; | ||
| }; | ||
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| ... | ||
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No. Please do not lie about maintainer.